This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-059122, filed Mar. 3, 2000; and No. 2001-050776, filed Feb. 26, 2001, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a semiconductor device such as a high voltage device. More specifically, the present invention relates to an LDMOS (lateral double-diffusion MOSFET) that is improved in ESD (electrostatic discharge) reliability.
Power ICs are generally constituted of both a low-voltage device and a high voltage device and widely used in, for example, the auto mobile applications. On-vehicle semiconductor devices are used in harsh environments and thus require relatively high-level protection against ESD and another type of electrical transient pulse. The ESD is considered to be a high-energy pulse caused when a person or a thing bearing electrical charges comes into contact with an integrated circuit. As one method of protecting a semiconductor device against the ESD, a resistance element can be inserted between a semiconductor element and an output pin to lower the level of a voltage. However, an LDMOS typically requires compatibility between low on-resistance and high breakdown voltage as power device. It is not therefore advisable to insert the resistance element because the low-on-resistance characteristic of the LDMOS is degraded.
FIG. 17 shows a prior art n-type LDMOS. In this LDMOS, an n+-type buried layer 12 is formed in a pxe2x88x92-type substrate 11. An n-type active layer 13 epitaxially grows on the buried layer 12. A p-type base layer 14 is selectively formed in the active layer 13, and an n+-type source layer 15 and a p+-type diffusion layer 14a are formed in the base layer 14. An n+-type drain layer 16 is formed at a distance from the base layer 14 of the active layer 13. A LOCOS oxide film 17 is formed in a surface area of the active layer 13 between the drain and base layers 16 and 14. A gate electrode (G) 18 is formed between the source layer 15 and the LOCOS oxide film 17 and above the active layer 13 and the base layer 14 with a gate insulation film (not shown) interposed therebetween. A source electrode (S) 19 is provided on the diffusion and source layers 14a and 15, while a drain electrode (D) 20 is provided on the drain layer 16.
In the above structure of the prior art LDMOS, when an intensive electric field is applied to the drain layer 16 by ESD, an avalanche breakdown occurs at one end portion of the drain layer 16, toward the LOCOS oxide film 17, to thereby generate electrons and holes. The electrons flow into the drain layer 16 from the end portion of the drain layer 16, while the holes flow into the base layer 14 therefrom. Thus, a parasitic bipolar transistor, which is constituted of the n+-type drain layer 16, p-type base layer 14, and n+-type source layer 15, turns on and accordingly the voltage between the source and drain layers is clamped to a lower one. However, current concentrates locally on the end portion of the drain layer 16, where a thermal runaway occurs. The prior art LDMOS therefore has the problem that adequate ESD reliability cannot be obtained and, in extreme cases, the drain layer is destroyed.
The present invention has been developed to resolve the above problem. An object of the present invention is to provide a semiconductor device capable of mitigating the concentration of current on an end portion of a drain layer under ESD stress and lowering a holding voltage more than that of the prior art LDMOS when a large amount of current flows, thereby improving in ESD reliability.
The above object is attained by the following device: A semiconductor device comprising: an active layer of a first conductivity type; a base layer of a second conductivity type formed in a surface area of the active layer; a source layer of the first conductivity type formed in a surface area of the base layer; a drain layer of the first conductivity type formed in the surface area of the active layer at a distance from the base layer; an anode layer of the second conductivity type formed adjacent to the drain layer between the base layer and the drain layer; a gate layer formed between the source layer and the drain layer and on the base layer with a gate insulation film interposed therebetween; a source electrode formed on a surface of the base layer and that of the source layer; and a drain electrode formed on a surface of the drain layer and that of the anode layer, wherein the anode layer constitutes a parasitic thyristor, together with the source layer, the base layer, and the active layer, when ESD occurs.
The semiconductor device described above mitigates the concentration of current on an end portion of the drain layer under ESD stress and lowers a holding voltage more than that of a prior art LDMOS when a large amount of current flows. The ESD reliability can be improved accordingly.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.